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CDC318ADL 参数 Datasheet PDF下载

CDC318ADL图片预览
型号: CDC318ADL
PDF下载: 下载PDF文件 查看货源
内容描述: 1线路至18线路时钟驱动器,带有I2C控制接口 [1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE]
分类和应用: 时钟驱动器
文件页数/大小: 12 页 / 184 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
D
D
D
D
D
D
D
D
D
D
High-Speed, Low-Skew 1-to-18 Clock Buffer
for Synchronous DRAM (SDRAM) Clock
Buffering Applications
Output Skew, t
sk(o)
, Less Than 250 ps
Pulse Skew, t
sk(p)
, Less Than 500 ps
Supports up to Four Unbuffered SDRAM
Dual Inline Memory Modules (DIMMs)
I
2
C Serial Interface Provides Individual
Enable Control for Each Output
Operates at 3.3 V
Distributed V
CC
and Ground Pins Reduce
Switching Noise
100-MHz Operation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
Packaged in 48-Pin Shrink Small Outline
(DL) Package
DL PACKAGE
(TOP VIEW)
description
The CDC318A is a high-performance clock buffer
designed to distribute high-speed clocks in PC
applications. This device distributes one input (A)
to 18 outputs (Y) with minimum skew for clock
distribution. The CDC318A operates from a 3.3-V
power supply. It is characterized for operation
from 0°C to 70°C.
This device has been designed with consideration
for optimized EMI performance. Depending on the
application layout, damping resistors in series to
the clock outputs (like proposed in the PC100
specification) may not be needed in most cases.
NC
NC
V
CC
1Y0
1Y1
GND
V
CC
1Y2
1Y3
GND
A
V
CC
2Y0
2Y1
GND
V
CC
2Y2
2Y3
GND
V
CC
5Y0
GND
V
CC
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
V
CC
4Y3
4Y2
GND
V
CC
4Y1
4Y0
GND
OE
V
CC
3Y3
3Y2
GND
V
CC
3Y1
3Y0
GND
V
CC
5Y1
GND
GND
SCLOCK
NC – No internal connection
The device provides a standard mode (100K-bits/s) I
2
C serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the I
2
C device address table. Both of the I
2
C inputs
(SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 kΩ).
Three 8-bit I
2
C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1