CDC318
1-LINE TO 18-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS587B – JANUARY 1997 – REVISED MARCH 1998
D
D
D
D
D
D
D
D
D
High-Speed, Low-Skew 1-to-18 Clock Buffer
for Synchronous DRAM (SDRAM) Clock
Buffering Applications
Output Skew, t
sk(o)
, Less Than 250 ps
Pulse Skew, t
sk(p)
, Less Than 650 ps
Supports up to Four Unbuffered SDRAM
Dual Inline Memory Modules (DIMMs)
I
2
C Serial Interface Provides Individual
Enable Control for Each Output
Operates at 3.3 V
Distributed V
CC
and Ground Pins Reduce
Switching Noise
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
Packaged in 48-Pin Shrink Small Outline
(DL) Package
DL PACKAGE
(TOP VIEW)
description
The CDC318 is a high-performance clock buffer
that distributes one input (A) to 18 outputs (Y) with
minimum skew for clock distribution. The CDC318
operates from a 3.3-V power supply, and is
characterized for operation from 0°C to 70°C.
The device provides a standard mode
(100K-bits/s) I
2
C serial interface for device
control. The implementation is as a slave/receiver.
The device address is specified in the I
2
C device
address table. Both of the I
2
C inputs (SDATA and
SCLOCK) provide integrated pullup resistors
(typically 140 kΩ) and are 5-V tolerant.
NC
NC
V
CC
1Y0
1Y1
GND
V
CC
1Y2
1Y3
GND
A
V
CC
2Y0
2Y1
GND
V
CC
2Y2
2Y3
GND
V
CC
5Y0
GND
V
CC
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
V
CC
4Y3
4Y2
GND
V
CC
4Y1
4Y0
GND
OE
V
CC
3Y3
3Y2
GND
V
CC
3Y1
3Y0
GND
V
CC
5Y1
GND
GND
SCLOCK
NC – No internal connection
Three 8-bit I
2
C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC318 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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