CDC391
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
SCAS334A – DECEMBER 1992 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
GND
500
Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
LOAD CIRCUIT FOR OUTPUTS
Output
Control
(low-level
enabling)
tPZL
3V
3V
1.5 V
1.5 V
0V
tPLZ
3.5 V
1.5 V
tPHZ
tPZH
1.5 V
VOH
VOH – 0.3 V
≈
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL + 0.3 V
VOL
Input
1.5 V
tPLH
1.5 V
0V
tPHL
2V
0.8 V
tr
1.5 V
2V
0.8 V
VOH
VOL
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
Output
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5