CDCF2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS628B – APRIL 1999 REVISED NOVEMBER 1999
TYPICAL CHARACTERISTICS
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
20
VCC = 3.3 V
fc = 133 MHz
C(LY) = 25pF
TA = 25°C
See Notes A and B
Phase Error
–10
–100
200
Phase Adjustment Slope – ps/pF
10
100
0
0
–20
–200
–30
Phase Adjustment Slope
–40
0
5
10
15
20
25
30
35
40
45
50
C(LF) – Lumped Feedback Capacitance at FBIN – pF
–300
–400
Figure 3
NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50
Ω
Phase error measured from CLK to Y
B. CLF = Lumped feedback capacitance at FBIN
PHASE ERROR
vs
CLOCK FREQUENCY
0
–50
–100
Phase Error – ps
–150
–200
–250
–300
–350
–400
–450
–500
50
60
70
80
90
100 110
120 130
140
VCC = 3.3 V
C(LY) = 25 pF
C(LF) = 12 pF
TA = 25°C
See Note A
Phase Error – ps
0
–50
–100
–150
–200
–250
–300
–350
–400
–450
–500
3
3.1
fc = 133 MHz
C(LY) = 25 pF
C(LF) = 12 pF
TA = 25°C
See Note A
PHASE ERROR
vs
SUPPLY VOLTAGE
3.2
Phase Error – ps
3.3
3.4
3.5
3.6
fc – Clock Frequency – MHz
VCC – Supply Voltage – V
Figure 4
NOTE A: Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50
Ω
Figure 5
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