TYPICAL CHARACTERISTICS: V
D
= V
A
= +3V
(Cont.)
At T
A
= +25°C, Differential I
OUT
= 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
FOUR-TONE OUTPUT SPECTRUM
0
–10
–20
Magnitude (dBm)
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
f
CLOCK
= 50MSPS
f
OUT1
= 6.25MHz
f
OUT2
= 6.75MHz
f
OUT3
= 7.25MHz
f
OUT4
= 7.75MHz
SFDR = 67dBc
Amplitude = 0dBFS
15
20
25
Frequency (MHz)
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC904 uses the current steering
technique to enable fast switching and a high update rate. The
core element within the monolithic DAC is an array of seg-
mented current sources that are designed to deliver a full-scale
output current of up to 20mA, as shown in Figure 1. An internal
decoder addresses the differential current switches each time
the DAC is updated and a corresponding output current is
formed by steering all currents to either output summing node,
I
OUT
or I
OUT
. The complementary outputs deliver a differential
output signal that improves the dynamic performance through
reduction of even-order harmonics, common-mode signals
(noise), and double the peak-to-peak output signal swing by a
factor of two, compared to single-ended operation.
The segmented architecture results in a significant reduction
of the glitch energy, and improves the dynamic performance
(SFDR) and DNL. The current outputs maintain a very high
output impedance of greater than 200kΩ.
The full-scale output current is determined by the ratio of the
internal reference voltage (1.24V) and an external resistor,
R
SET
. The resulting I
REF
is internally multiplied by a factor of
32 to produce an effective DAC output current that can range
from 2mA to 20mA, depending on the value of R
SET
.
The DAC904 is split into a digital and an analog portion, each
of which is powered through its own supply pin. The digital
section includes edge-triggered input latches and the de-
coder logic, while the analog section comprises the current
source array with its associated switches and the reference
circuitry.
+3V to +5V
Analog
0.1µF
(1)
+3V to +5V
Digital
Bandwidth
Control
DAC904
Full-Scale
Adjust
Resistor
+V
A
BW
+V
D
I
OUT
FSA
Ref
Input REF
IN
0.1µF
INT/EXT
Ref
Buffer
Ref
Control
Amp
PMOS
Current
Source
Array
LSB
Switches
Segmented
MSB
Switches
BYP
I
OUT
1:1
V
OUT
R
SET
2kΩ
400pF
50Ω
0.1µF
20pF
(1)
50Ω
20pF
(1)
Latches and Switch
Decoder Logic
PD
Power Down
(internal pull-down)
+1.24V Ref
AGND
Analog
Ground
CLK
Clock
Input
14-Bit Data Input
D13...D0
DGND
Digital
Ground
NOTE: Supply bypassing not shown.
NOTE: (1) Optional.
FIGURE 1. Functional Block Diagram of the DAC904.
10
DAC904
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SBAS095C
TI [ TEXAS INSTRUMENTS ]
