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................................................................................................................................................................
SLLS755H – JULY 2006 – REVISED MAY 2008
PARAMETER MEASUREMENT INFORMATION
ISOLATION BARRIER
V
CC
1
V
I
OUT
t
PLH
V
O
C
L
NOTE B
V
O
50%
tr
90%
10%
tf
V
CC
1/2
V
CC
1/2
0V
t
PHL
V
OH
50%
V
OL
IN
Input
Generator
NOTE A
V
I
50
W
A.
B.
The input pulse is supplied by a generator having the following characteristics: PRR
≤
50 kHz, 50% duty cycle, t
r
≤
3
ns, t
f
≤
3 ns, Z
O
= 50Ω.
C
L
= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
V
I
ISOLATION BARRIER
V
CC
1
0V
or
V
CC
1
IN
V
CC
1
OUT
V
I
V
O
C
L
NOTE A
t
fs
V
O
50%
2.7 V
0V
V
OH
FAILSAFE HIGH
V
OL
A.
C
L
= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
CC
1
C = 0.1
m
F± 1%
ISOLATION BARRIER
V
CC
2
C = 0.1
m
F± 1%
Pass-fail criteria:
Output must
remain stable
S1
IN
OUT
NOTE A
V
OH
or V
OL
GND1
V
CM
GND2
A.
C
L
= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit
DUT
Tektronix
HFS9009
IN
V
CC
1
OUT
PATTERN
GENERATOR
Tektronix
784D
0V
V
CC
/2
Jitter
NOTE: PRBS bit pattern run length is 2
16
– 1. Transition time is 800 ps.
Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
Copyright © 2006–2008, Texas Instruments Incorporated
11
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