SNVS543I – JANUARY 2008 – REVISED MAY 2013
Delay Mask Counter
EN1
RDY1
EN2
RDY2
POR
S
R
Q
Q
Delay
NPOR
Delay Mask Counter
Figure 31. Design Implementation of the Flexible Power-On Reset
Design implementation of the flexible power-on reset. An internal power-on reset of the IC is used with EN1 and
EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to
generate the set signal (HIGH) to the delay timer. S=R=1 never occurs. The mask timers are triggered off EN1
and EN2 which are gated with RDY1, and RDY2 to generate outputs to the final AND gate to generate the
nPOR.
Under Voltage Lock Out
The LM26480 features an “under voltage lock out circuit”. The function of this circuit is to continuously monitor
the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this
supply voltage is less than 2.8 VDC.
The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 VDC
trip point for a V
IN
OK – Not OK detector. This V
IN
OK signal is then used to gate the enable signals to the four
regulators of the LM26480. When VINLDO12 is greater than 2.8 VDC the four
enables
control the four
regulators, when VINLDO12 is less than 2.8 VDC the four regulators are
disabled
by the V
IN
detector being in
the “Not OK” state. The circuit has built in hysteresis to prevent chattering occurring.
Application Notes
External Component Selection
LDO
0.47
µF
R1
LDO_FB
R2
Buck
LM26480
Buck_FB
C1
C2
R1
10
µF
R2
Ideal Resistor Values
Target
R2 (KΩ)
Vout (V) R1 (KΩ)
0.8
0.9
22
120
160
200
200
Common R Values
R1 (KΩ)
121
162
R2 (KΩ)
200
200
Actual VOUT
W/ Com/R (V)
0.803
0.905
Actual VOUT
Delta from
Target (V)
0.002
0.005
Feedback Capacitors
C1(pF)
15
15
C2(pF)
none
none
Buck1
Only
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