SNVS219K – JUNE 2003 – REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
Voltages from the indicated pins to SGND/PGND:
VIN, ILIM1, ILIM2, KS1, KS2
SW1, SW2, RSNS1, RSNS2
FB1, FB2, VDD1, VDD2
SYNC, COMP1, COMP2, UV Delay
ON/SS1, ON/SS2
(3)
−0.3V
to 38V
−0.3
to (V
IN
+ 0.3)V
−0.3V
to 6V
−0.3V
to (VLIN5 +0.3)V
−0.3V
to (VLIN5 +0.6)V
43V
−0.3V
to 7V
−0.3V
to (VDD+0.3)V
−0.3V
+0.3V
1.1W
3.4W
−65°C
to +150°C
Wave
Infrared
Vapor Phase
4 sec, 260°C
10sec, 240°C
75sec, 219°C
2kV
CBOOT1, CBOOT2
CBOOT1 to SW1, CBOOT2 to SW2
LDRV1, LDRV2
HDRV1 to SW1, HDRV2 to SW2
HDRV1 to CBOOT1, HDRV2 to CBOOT2
Power Dissipation (T
A
= 25°C)
TSSOP
HTSSOP
Ambient Storage Temp. Range
Soldering Dwell Time, Temp.
(5)
(4)
ESD Rating
(1)
(6)
(2)
(3)
(4)
(5)
(6)
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
ON/SS1 and ON/SS2 are internally pulled up to one diode drop above VLIN5. Do not apply an external pull-up voltage to these pins. It
may cause damage to the IC.
The maximum allowable power dissipation is calculated by using P
DMAX
= (T
JMAX
- T
A
)/θ
JA
, where T
JMAX
is the maximum junction
temperature, T
A
is the ambient temperature and
θ
JA
is the junction-to-ambient thermal resistance of the specified package. The power
dissipation ratings results from using 125°C, 25°C, and 90.6°C/W for T
JMAX
, T
A
, and
θ
JA
respectively. A
θ
JA
of 90.6°C/W represents the
worst-case condition of no heat sinking of the 28-pin TSSOP. The HTSSOP package has a
θ
JA
of 29°C/W. The HTSSOP package
thermal ratings results from the IC being mounted on a 4 layer JEDEC standard board using the same temperature conditions as the
TSSOP package above. A thermal shutdown will occur if the temperature exceeds the maximum junction temperature of the device.
See
for other methods of soldering plastic small-outline packages.
For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5 kΩ resistor.
(1)
OPERATING RATINGS
VIN (VLIN5 tied to VIN)
VIN (VIN and VLIN5 separate)
Junction Temperature
(1)
4.5V to 5.5V
5.5V to 36V
−40°C
to +125°C
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
4
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