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LMK04828BISQX/NOPB 参数 Datasheet PDF下载

LMK04828BISQX/NOPB图片预览
型号: LMK04828BISQX/NOPB
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内容描述: LMK0482xB超低噪音,符合JESD204B时钟抖动清除器与双回路锁相环 [LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs]
分类和应用: 时钟
文件页数/大小: 101 页 / 2232 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SNAS605 AP – MARCH 2013 – REVISED JUNE 2013
LMK0482xB
Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner with Dual Loop PLLs
Check for Samples:
1 INTRODUCTION
1.1
12
Features
– Integrated Low-Noise Crystal Oscillator
Circuit
– Holdover mode when input clocks are lost
PLL2
– Normalized [1 Hz] PLL noise floor of
–227 dBc/Hz
– Phase detector rate up to 155 MHz
– OSCin frequency-doubler
– Two Integrated Low-Noise VCOs
50% duty cycle output divides, 1 to 32 (even
and odd)
Precision digital delay, dynamically adjustable
25 ps step analog delay
Multi-mode: Dual PLL, single PLL, and clock
distribution in 0 delay option
Industrial Temperature Range: –40 to 85°C
3.15 V to 3.45 V operation
Package: 64-pin QFN (9.0 x 9.0 x 0.8 mm)
Device
LMK04826
LMK04828
VCO0 Frequency
1840 to 1970 MHz
2370 to
2630 MHz
VCO1 Frequency
2440 to 2505 MHz
2920 to 3080 MHz
• JEDEC JESD204B Support
• Ultra-Low RMS Jitter and Performance
– 88 fs RMS jitter (12 kHz to 20 MHz)
– 91 fs RMS jitter (100 Hz to 20 MHz)
– –162.5 dBc/Hz noise floor at 245.76 MHz
• Up to 14 Differential Device Clocks from PLL2
– Up to 7 SYSREF Clocks
– Maximum clock output frequency 3.1 GHz
– LVPECL, LVDS, HSDS, LCPECL
programmable outputs from PLL2
• Up to 1 buffered VCXO/Crystal output from
PLL1
– LVPECL, LVDS, 2xLVCMOS programmable
• Dual Loop PLLatinum™ PLL Architecture
• PLL1
– Up to 3 redundant input clocks
• Automatic and manual switch-over
modes
• Hitless switching and LOS
Recovered
³GLUW\´ FORFN RU
clean clock
Crystal or
VCXO
CLKin0
OSCout
LMX2581
PLL+VCO
0XOWLSOH ³FOHDQ´
clocks at different
frequencies
DCLKout12
Backup
Reference
Clock
CLKin1
SDCLKout13
FPGA
LMK0482xB
DCLKout8 &
DCLKout10
SDCLKout9 &
SDCLKout11
DCLKout0 &
DCLKout2
ADC
DCLKout4,
SDCLKout5
SDCLKout1 &
SDCLKout3
DAC
DAC
Serializer/
Deserializer
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PLLatinum is a trademark of Texas Instruments.
Copyright © 2013, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.