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MSP430F5336IZQWR 参数 Datasheet PDF下载

MSP430F5336IZQWR图片预览
型号: MSP430F5336IZQWR
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号微控制器 [MIXED SIGNAL MICROCONTROLLER]
分类和应用: 微控制器
文件页数/大小: 101 页 / 918 K
品牌: TI [ TEXAS INSTRUMENTS ]
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MSP430F533x
SLAS721B – AUGUST 2010 – REVISED AUGUST 2012
Table 3. Terminal Functions (continued)
TERMINAL
NAME
P2.1/P2MAP1
NO.
PZ
18
ZQW
H2
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
P2.4/P2MAP4
21
J2
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
Digital power supply
Digital ground supply
Regulated core power supply (internal use only, no external current loading)
I/O
General-purpose digital I/O
Digital ground supply
Do not connect. It is strongly recommended to leave this terminal open.
I/O
I/O
I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O with port interrupt
Timer TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
P1.1/TA0.0
35
M5
I/O
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
P1.2/TA0.1
36
J6
I/O
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4
39
L6
I/O
General-purpose digital I/O with port interrupt
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
I/O
(1)
DESCRIPTION
P2.2/P2MAP2
19
J1
I/O
P2.3/P2MAP3
20
H4
I/O
P2.5/P2MAP5
22
K1
I/O
P2.6/P2MAP6
23
K2
I/O
P2.7/P2MAP7
DVCC1
DVSS1
VCORE
P5.2
DVSS
DNC
P5.3
P5.4
P5.5
(2)
24
25
26
27
28
29
30
31
32
33
L2
L1
M1
M2
L3
M3
J4
L4
M4
J5
I/O
P1.0/TA0CLK/ACLK
34
L5
I/O
P1.3/TA0.2
37
H6
I/O
P1.4/TA0.3
38
M6
I/O
P1.6/TA0.1
40
J7
I/O
(2)
8
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C
VCORE
.
Copyright © 2010–2012, Texas Instruments Incorporated