MSP430F563x
SLAS650C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Functional Block Diagram, MSP430F5632, MSP430F5631, MSP430F5630
PA
PB
PC
PD
XIN XOUT
DVCC DVSS
AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
P9.x
XT2IN
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5/P6
2×8 I/Os
16KB
RAM
I/O Ports
P7/P8
1×6 I/Os
1×8 I/Os
ACLK
Power
Management
SYS
I/O Ports
P9
1×8 I/Os
Unified
Clock
System
USCI0,1
USB
256KB
192KB
128KB
XT2OUT
Watchdog
SMCLK
Ax: UART,
IrDA, SPI
+2KB RAM
USB Buffer
Full-speed
LDO
SVM/SVS
Brownout
P2 Port
Mapping
Controller
Flash
PE
1×8 I/Os
Bx: SPI, I2C
MCLK
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
+8B Backup
RAM
PD
1×14 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
DMA
TA1 and
TA2
RTC_B
6 Channel
REF
TA0
TB0
JTAG/
SBW
Interface/
Comp_B
MPY32
CRC16
2 Timer_A
each with
3 CC
Reference
1.5V, 2.0V,
2.5V
Timer_A
5 CC
Registers
Timer_B
7 CC
Registers
Battery
Backup
System
Port PJ
Registers
4
Copyright © 2010–2012, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
