MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Functional Block Diagram, MSP430F673xIPZ, MSP430F672xIPZ
XIN
XOUT
DVCC DVSS
AVCC AVSS
AUX1 AUX2 AUX3
RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
P5.x P6.x
P7.x
PD
P8.x
PE
P9.x
(32kHz)
ACLK
Unified
Clock
System
SMCLK
MCLK
Flash
128kB
96KB
64KB
32KB
16KB
8kB
4KB
2KB
1KB
RAM
SYS
Watchdog
Port
Mapping
Controller
CRC16
MPY32
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
2×8 I/Os
I/O Ports
P9
1×4 I/O
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PE
1×4 I/O
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 3+1)
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
SD24_B
3 Channel
2 Channel
ADC10_A
10 Bit
200 KSPS
LCD_C
8MUX
Up to 320
Segments
REF
Reference
1.5V, 2.0V,
2.5V
RTC_C
JTAG/
SBW
Interface/
Port PJ
TA0
Timer_A
3 CC
Registers
TA1
TA2
TA3
Timer_A
2 CC
Registers
eUSCI_A0
eUSCI_A1
eUSCI_A2
(UART,
IrDA,SPI)
eUSCI_B0
(SPI, I2C)
DMA
3 Channel
PJ.x
Functional Block Diagram, MSP430F673xIPN, MSP430F672xIPN
XIN
XOUT
DVCC DVSS
AVCC AVSS
AUX1 AUX2 AUX3
RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
P5.x P6.x
(32kHz)
ACLK
Unified
Clock
System
SMCLK
MCLK
128KB
96KB
64KB
32KB
16KB
Flash
8KB
4KB
2KB
1KB
RAM
SYS
DMA
3 Channel
Watchdog
Port
Mapping
Controller
CRC16
MPY32
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 3+1)
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
SD24_B
3 Channel
2 Channel
ADC10_A
10 Bit
200 KSPS
LCD_C
8MUX
Up to 320
Segments
REF
Reference
1.5V, 2.0V,
2.5V
RTC_C
TA0
Timer_A
3 CC
Registers
JTAG/
SBW
Interface/
Port PJ
TA1
TA2
TA3
Timer_A
2 CC
Registers
eUSCI_A0
eUSCI_A1
eUSCI_A2
(UART,
IrDA,SPI)
eUSCI_B0
(SPI, I2C)
PJ.x
4
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