MSP430FR573x
MSP430FR572x
SLAS639
–
APRIL 2011
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at V
CC
to V
SS
Voltage applied to any pin (excluding VCORE)
Diode current at any device pin
Storage temperature range, T
stg
(3) (4) (5)
(2)
–0.3
V to 4.1 V
–0.3
V to V
CC
+ 0.3 V
±2
mA
–40°C
to 125°C
95°C
Maximum junction temperature, T
J
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under
"absolute
maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
"recommended
operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to V
SS
. V
CORE
is for internal device usage only. No external DC loading or voltage should be applied.
Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, T
stg
.
For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels. If hand soldering is required for application
prototyping, peak temperature must not exceed 250°C for a total of 5 minutes for any single device.
Programming of devices with user application code should only be performed post reflow/hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
Recommended Operating Conditions
MIN
V
CC
V
SS
T
A
T
J
CVCORE
CVCC/
CVCORE
Supply voltage during program execution and FRAM
programming(AV
CC
= DV
CC
)
(1)
Supply voltage (AV
SS
= DV
SS
)
Operating free-air temperature
Operating junction temperature
Required capacitor at VCORE
Capacitor ratio of VCC to VCORE
No FRAM wait states
2.0 V
≤
V
CC
≤
3.6 V
f
SYSTEM
Processor frequency (maximum MCLK frequency)
(2)
With FRAM wait states
NACCESS = {1},
NPRECHG = {2}
2.0 V
≤
V
CC
≤
3.6 V
10
0
8.0
MHz
0
24.0
I version
I version
–40
–40
470
2.0
0
85
85
NOM
MAX
3.6
UNIT
V
V
°C
°C
nF
(1)
(2)
It is recommended to power AV
CC
and DV
CC
from the same source. A maximum difference of 0.3 V between AV
CC
and DV
CC
can be
tolerated during power up and operation.
Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
Copyright
©
2011, Texas Instruments Incorporated
43
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