MSP430F530x, MSP430F5310
SLAS677B
–
SEPTEMBER 2010
–
REVISED MARCH 2011
Functional Block Diagram
–
MSP430F5304IRGZ, MSP430F5304IPT
XIN XOUT RST/NMI
DV
CC
DV
SS
V
CORE
AV
CC
AV
SS
P1.x
PA
P2.x
P3.x
PB
P4.x
P5.x
PC
P6.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
8KB
Flash
6KB
RAM
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
MCLK
I/O Ports
P1/P2
1×8 I/Os
1×1 I/Os
Interrupt
& Wakeup
PA
1×9 I/Os
I/O Ports
P4
1×8 I/Os
I/O Ports
P5/P6
1×6 I/Os
1×4 I/Os
PC
1×10 I/Os
REF
ADC10_A
10 Bit
200 KSPS
8 Channels
(6 int/ 2 ext)
Window
Comparator
PB
1×8 I/Os
CPUXV2
and
Working
Registers
MAB
MDB
DMA
3 Channel
EEM
(S:3+1)
USCI0
JTAG/
SBW
Interface
TA0
MPY32
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TA2
Timer_A
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
PU Port
LDO
PU.0, PU.1
Copyright
©
2010–2011, Texas Instruments Incorporated
7
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