SPRS586C
–
JUNE 2009
–
REVISED MAY 2011
OMAP-L138 C6-Integra™ DSP+ARM® Processor
Check for Samples:
1 OMAP-L138 C6-Integra™ DSP+ARM® Processor
1.1
12
Features
–
Normalization, Saturation, Bit-Counting
–
Compact 16-Bit Instructions
•
C674x Two Level Cache Memory Architecture
–
32K-Byte L1P Program RAM/Cache
–
32K-Byte L1D Data RAM/Cache
–
256K-Byte L2 Unified Mapped RAM/Cache
–
Flexible RAM/Cache Partition (L1 and L2)
•
Enhanced Direct-Memory-Access Controller 3
(EDMA3):
–
2 Channel Controllers
–
3 Transfer Controllers
–
64 Independent DMA Channels
–
16 Quick DMA Channels
–
Programmable Transfer Burst Size
•
TMS320C674x Floating-Point VLIW DSP Core
–
Load-Store Architecture With Non-Aligned
Support
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64 General-Purpose Registers (32 Bit)
–
Six ALU (32-/40-Bit) Functional Units
•
Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
•
Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
•
Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
–
Two Multiply Functional Units
•
Mixed-Precision IEEE Floating Point
Multiply Supported up to:
–
2 SP x SP
→
SP Per Clock
–
2 SP x SP
→
DP Every Two Clocks
–
2 SP x DP
→
DP Every Three Clocks
–
2 DP x DP
→
DP Every Four Clocks
•
Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
–
Instruction Packing Reduces Code Size
–
All Instructions Conditional
–
Hardware Support for Modulo Loop
•
Highlights
–
Dual Core SoC
•
375/456-MHz ARM926EJ-S™ RISC MPU
•
375/456-MHz C674x Fixed/Floating-Point
VLIW DSP
–
Enhanced Direct-Memory-Access Controller
(EDMA3)
–
Serial ATA (SATA) Controller
–
DDR2/Mobile DDR Memory Controller
–
Two Multimedia Card (MMC)/Secure Digital
(SD) Card Interface
–
LCD Controller
–
Video Port Interface (VPIF)
–
10/100 Mb/s Ethernet MAC (EMAC)
–
Programmable Real-Time Unit Subsystem
–
Three Configurable UART Modules
–
USB 1.1 OHCI (Host) With Integrated PHY
–
USB 2.0 OTG Port With Integrated PHY
–
One Multichannel Audio Serial Port
–
Two Multichannel Buffered Serial Ports
•
Dual Core SoC
–
375/456-MHz ARM926EJ-S™ RISC MPU
–
375/456-MHz C674x Fixed/Floating-Point
VLIW DSP
•
ARM926EJ-S Core
–
32-Bit and 16-Bit (Thumb®) Instructions
–
DSP Instruction Extensions
–
Single Cycle MAC
–
ARM® Jazelle® Technology
–
EmbeddedICE-RT™ for Real-Time Debug
•
ARM9 Memory Architecture
–
16K-Byte Instruction Cache
–
16K-Byte Data Cache
–
8K-Byte RAM (Vector Table)
–
64K-Byte ROM
•
C674x™ Instruction Set Features
–
Superset of the C67x+™ and C64x+™ ISAs
–
Up to 3648/2746 C674x MIPS/MFLOPS
–
Byte-Addressable (8-/16-/32-/64-Bit Data)
–
8-Bit Overflow Protection
–
Bit-Field Extract, Set, Clear
1
2
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PRODUCTION DATA information is current as of publication date.
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