1/f
S
LRCIN (pin 19)
BCKIN (pin 17)
AUDIO DATA WORD = 16-BIT
DIN (pin 18)
1
2
3
MSB
1
2
3
MSB
1
2
3
MSB
14
LSB
18
LSB
22
LSB
23 24
1
2
19 20
1
2
15 16
1
2
3
MSB
3
MSB
3
MSB
14
LSB
18
LSB
22
LSB
23 24
1
2
19 20
1
2
15 16
1
2
L_ch
R_ch
AUDIO DATA WORD = 20-BIT
DIN (pin 18)
AUDIO DATA WORD = 24-BIT
DIN (pin 18)
FIGURE 6. I
2
S Data Input Timing.
LRCKIN
t
BCH
BCKIN
t
BCY
DIN
t
DS
t
DH
t
BL
t
BCL
t
LB
1.4V
1.4V
1.4V
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
: t
BCY
: t
BCH
: t
BCL
: 100ns (min)
: 50ns (min)
: 50ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
BCKIN Rising Edge to LRCIN Edge : t
BL
LRCIN Edge to BCKIN Rising Edge : t
LB
DIN Set-up Time
DIN Hold Time
: t
DS
: t
DH
FIGURE 7. Audio Data Input Timing.
system clock is specified at 150ps typical. Figure 3 illus-
trates the timing requirements for the 27MHz master clock.
Figure 4 illustrates the system clock connections for an
external clock or crystal oscillator.
The PCM1727 internal PLL can be programmed for three
different sampling frequencies (LRCIN), as shown in Table
I. The internal sampling clocks generated by the various
programmed frequencies are shown in Table II. The system
clock output frequency for PCM1727 is 100% accurate.
To provide MCKO clock and SCKO1, SCKO2, SCKO3
clocks for external circuits, an external buffer may be used
to avoid degrading audio performance (as shown in the
connection diagram, in Figure 1).
Sampling Frequencies-LRCIN (kHz)
Standard Sampling Freq
Double of Standard Sampling Freq
44.1
48
96
TABLE I. Sampling Frequencies.
Sampling
Frequency
(LRCIN)
44.1kHz
48kHz
96kHz
Standard
Standard
Double
SCKO2
System Clock
16.9344MHz
18.4320MHz
36.8640MHz
SCKO3
System Clock
33.8688MHz
36.8640MHz
36.8640MHz
TABLE II. Sampling Frequencies vs Internal System Clock
(= Output Frequencies of Dual PLL).
8
PCM1727
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