RM48L930
RM48L730
RM48L530
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SPNS176–SEPTEMBER 2011
5.9.5 SPI Slave Mode I/O Timings
Table 5-21. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO.
1
Parameter
tc(SPC)S
MIN
40
MAX
Unit
ns
Cycle time, SPICLK(5)
256tc(VCLK)
2(6)
tw(SPCH)S
tw(SPCL)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
14
ns
14
3(6)
4(6)
tw(SPCL)S
14
ns
ns
tw(SPCH)S
td(SPCH-SOMI)S
14
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
trf(SOMI) + 18
trf(SOMI) + 18
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
th(SPCL-SIMO)S
th(SPCH-SIMO)S
td(SPCL-SENAH)S
td(SPCH-SENAH)S
td(SCSL-SENAL)S
Delay time, SPISOMI valid after SPICLK low (clock polarity
= 1)
5(6)
6(6)
7(6)
8
Hold time, SPISOMI data valid after SPICLK high (clock
polarity =0)
2
ns
ns
ns
ns
ns
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
2
Setup time, SPISIMO before SPICLK low (clock polarity =
0)
2
Setup time, SPISIMO before SPICLK high (clock polarity =
1)
2
2
Hold time, SPISIMO data valid after SPICLK low (clock
polarity = 0)
Hold time, SPISIMO data valid after S PICLK high (clock
polarity = 1)
2
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 0)
1.5tc(VCLK)
1.5tc(VCLK)
tf(ENAn)
2.5tc(VCLK)+tr(ENAn)
Delay time, SPIENAn high after last SPICLK high (clock
polarity = 1)
2.5tc(VCLK)+
tr(ENAn)
9
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
tc(VCLK)+tf(ENAn)+1
4
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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