SPNS176
–
SEPTEMBER 2011
Table 3-2. Output Buffer Drive Strengths (continued)
Low-level Output Current,
I
OL
for V
I
=V
OLmax
or
High-level Output Current,
I
OH
for V
I
=V
OHmin
AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,
DMM_CLK, DMM_DATA[0], DMM_DATA[1], DMM_nENA, DMM_SYNC,
GIOA[0-7], GIOB[0-7],
2mA zero-dominant
LINRX, LINTX,
MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA,
MIBSPI5NCS[0-3], MIBSPI5NENA,
N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7],
N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14],
N2HET2[15], N2HET2[16], N2HET2[18],
SPI2NCS[0], SPI2NENA, SPI4NCS[0], SPI4NENA
ECLK,
SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8mA for these signals.
Signals
3.8
Input Timings
t
pw
Input
V
IL
V
IH
V
IH
V
IL
V
CCIO
0
Figure 3-2. TTL-Level Inputs
Table 3-3. Timing Requirements for Inputs
(1)
Parameter
t
pw
(1)
(2)
Input minimum pulse width
t
c(VCLK)
= peripheral VBUS clock cycle time = 1 / f
(VCLK)
The timing shown above is only valid for pin used in GIO mode.
MIN
t
c(VCLK)
+ 10
(2)
MAX
Unit
ns
3.9
Output Timings
Table 3-4. Switching Characteristics for Output Timings versus Load Capacitance (CL)
Parameter
MIN
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
MAX
2.5
4
7.2
12.5
2.5
4
7.2
12.5
ns
Unit
ns
Rise time, t
r
8mA low EMI pins
(see
Fall time, t
f
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
Copyright
©
2011, Texas Instruments Incorporated
Device Operating Conditions
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selectable 8mA / 2mA
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