SPNS176
–
SEPTEMBER 2011
4.4
Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
4.4.1
Causes of Warm Reset
Table 4-5. Causes of Warm Reset
DEVICE EVENT
SYSTEM STATUS FLAG
Exception Status Register, bit 15
Global Status Register, bit 0
Global Status Register, bits 8 and 9
Exception Status Register, bit 13
Exception Status Register, bit 5
Exception Status Register, bit 4
Exception Status Register, bit 3
Power-Up Reset
Oscillator fail
PLL slip
Watchdog exception / Debugger reset
CPU Reset (driven by the CPU STC)
Software Reset
External Reset
PRODUCT PREVIEW
4.4.2
nRST Timing Requirements
Table 4-6. nRST Timing Requirements
(1)
PARAMETER
MIN
1180 t
c(OSC)
+ 1048t
c(OSC)
8t
c(VCLK)
500
2000
ns
MAX
UNIT
ns
t
v(RST)
Valid time, nRST active after
nPORRST inactive
Valid time, nRST active (all other
System reset conditions)
t
f(nRST)
Filter time nRST pin;
pulses less than MIN will be
filtered out, pulses greater than
MAX will generate a reset
(1)
Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load
capacitance table.
50
System Information and Electrical Specifications
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2011, Texas Instruments Incorporated
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