SPNS175
–
SEPTEMBER 2011
RM48Lx40 16/32-Bit RISC Flash Microcontroller
1 RM48Lx40 16/32-Bit RISC Flash Microcontroller
1.1
1
Features
•
Multiple Communication Interfaces
–
10/100 Mbps Ethernet MAC (EMAC)
•
IEEE 802.3 compliant (3.3V-I/O only)
•
Supports MII and MDIO
–
Three CAN Controllers (DCAN)
•
64 mailboxes with parity protection each
•
Compliant to CAN protocol version 2.0B
–
Inter-Integrated Circuit (I
2
C)
–
Three Multi-buffered Serial Peripheral
Interfaces (MibSPI)
•
128 Words with Parity Protection each
–
Two Standard Serial Peripheral Interfaces
(SPI)
–
Local Interconnect Network Interface (LIN)
Controller
•
Compliant to LIN protocol version 2.1
–
Standard Serial Communication Interface
(SCI)
•
Two High-End Timer Modules (N2HET)
–
N2HET1: 32 programmable channels
–
N2HET2: 20 programmable channels
–
160 Word Instruction RAM with parity
protection each
–
Each includes Hardware Angle Generator
–
Dedicated Transfer Unit for each N2HET
(HTU)
•
Two 10/12-bit Multi-Buffered ADC Modules
–
ADC1: 24 channels
–
ADC2: 16 channels
–
16 shared channels
–
64 result buffers with parity protection each
•
Packages
–
144-pin Quad Flatpack (PGE) [Green]
–
337-Ball Grid Array (ZWT) [Green]
•
High-Performance Microcontroller for Safety
Critical Applications
–
Dual CPU’s running in lockstep
–
ECC on flash and RAM interfaces
–
Built-In Self Test for CPU and on-chip RAMs
–
Error Signaling Module with Error Pin
–
Voltage and Clock Monitoring
•
ARM® Cortex™
–
R4F 32-bit RISC CPU
–
Efficient 1.6DMIPS/MHz with 8-stage pipeline
–
Floating-Point Unit with Single/Double
Precision
–
12-Region Memory Protection Unit
–
Open Architecture with 3rd Party Support
•
Operating Conditions
–
Up to 200MHz System Clock
–
Core Supply Voltage (VCC): 1.2V nominal
–
I/O Supply Voltage (VCCIO): 3.3V nominal
•
Integrated Memory
–
Up to 3MB Program Flash with ECC
–
Up to 256KB RAM with ECC
–
64KB Flash for emulated EEPROM
•
16- bit External Memory Interface
•
Common Platform Architecture
–
Consistent memory map across family
–
Real-Time Interrupt Timer (RTI) OS Timer
–
96-channel Vectored Interrupt Module (VIM)
–
2-channel Cyclic Redundancy Checker (CRC)
•
Direct Memory Access (DMA) Controller
–
16 Channels and 32 Control Packets
–
Parity protection for control packet RAM
–
DMA Accesses Protected by Dedicated MPU
•
Frequency-Modulated Phase-Locked-Loop
(FMPLL) with Built-In Slip Detector
•
Separate Non-Modulating PLL
•
IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight Components
•
JTAG Security Module
•
Trace and Calibration Capabilities
–
Embedded Trace Macrocell (ETM-R4)
–
Data Modification Module (DMM)
–
RAM Trace Port (RTP)
–
Parameter Overlay Module (POM)
1
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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to change or discontinue these products without notice.
Copyright
©
2011, Texas Instruments Incorporated
PRODUCT PREVIEW
TI [ TEXAS INSTRUMENTS ]
