RM48L940
RM48L740
RM48L540
SPNS175–SEPTEMBER 2011
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2.4.2 ZWT Package
2.4.2.1 Multi-Buffered Analog-to-Digital Converters (MibADC)
Table 2-22. ZWT Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
ADREFHI(1)
V15
Input
-
-
-
ADC high reference
supply
ADREFLO(1)
VCCAD(1)
VSSAD
V16
W15
V19
Input
Power
Ground
ADC low reference supply
Operating supply for ADC
ADC supply power
-
W16
W18
W19
N19
AD1EVT/MII_RX_ER
Input Pull Down Programmable, ADC1 event trigger input,
20uA or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]
V10
I/O
Pull Up
Programmable, ADC2 event trigger input,
20uA
or GIO
AD1IN[0]
W14
V17
V18
T17
U18
R17
T19
V14
P18
W17
U17
U19
T16
T18
R18
P19
V13
U13
U14
U16
U15
T15
R19
R16
Input
-
-
ADC1 analog input
AD1IN[01]
AD1IN[02]
AD1IN[03]
AD1IN[04]
AD1IN[05]
AD1IN[06]
AD1IN[07]
AD1IN[08] / AD2IN[08]
AD1IN[09] / AD2IN[09]
AD1IN[10] / AD2IN[10]
AD1IN[11] / AD2IN[11]
AD1IN[12] / AD2IN[12]
AD1IN[13] / AD2IN[13]
AD1IN[14] / AD2IN[14]
AD1IN[15] / AD2IN[15]
AD1IN[16] / AD2IN[0]
AD1IN[17] / AD2IN[01]
AD1IN[18] / AD2IN[02]
AD1IN[19] / AD2IN[03]
AD1IN[20] / AD2IN[04]
AD1IN[21] / AD2IN[05]
AD1IN[22] / AD2IN[06]
AD1IN[23] / AD2IN[07]
Input
-
-
ADC1/ADC2 shared
analog inputs
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
22
Device Package and Terminal Functions
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