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SN74ACT373PWRE4 参数 Datasheet PDF下载

SN74ACT373PWRE4图片预览
型号: SN74ACT373PWRE4
PDF下载: 下载PDF文件 查看货源
内容描述: 八路D型透明锁存器带3态输出 [OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS]
分类和应用: 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
文件页数/大小: 17 页 / 658 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SN54ACT373, SN74ACT373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS544E – OCTOBER 1995 – REVISED OCTOBER 2002
D
D
D
D
4.5-V to 5.5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 10 ns at 5 V
Inputs Are TTL-Voltage Compatible
SN54ACT373 . . . J OR W PACKAGE
SN74ACT373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in bus-organized systems without need for
interface or pullup components.
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54ACT373 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
3
4
5
6
7
8
2D
2Q
3Q
3D
4D
2 1 20 19
18
17
16
15
8Q
8D
7D
7Q
6Q
6D
14
9 10 11 12 13
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PDIP – N
SOIC – DW
–40°C to 85°C
40°C
SOP – NS
SSOP – DB
TSSOP – PW
CDIP – J
–55°C to 125°C
CFP – W
LCCC – FK
PACKAGE†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74ACT373N
SN74ACT373DW
SN74ACT373DWR
SN74ACT373NSR
SN74ACT373DBR
SN74ACT373PWR
SNJ54ACT373J
SNJ54ACT373W
SNJ54ACT373FK
TOP-SIDE
MARKING
SN74ACT373N
ACT373
ACT373
AD373
AD373
SNJ54ACT373J
SNJ54ACT373W
SNJ54ACT373FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4Q
GND
LE
5Q
5D
1