SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
D
D
D
D
D
D
Bus Transceivers/Registers
Independent Registers and Enables for A
and B Buses
Multiplexed Real-Time and Stored Data
Choice of True or Inverting Data Paths
Choice of 3-State or Open-Collector
Outputs to A Bus
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
DEVICE
A OUTPUT
3 State
B OUTPUT
3 State
LOGIC
Inverting
SN54ALS’, SN54AS’ . . . JT PACKAGE
SN74ALS’, SN74AS’ . . . DW OR NT PACKAGE
(TOP VIEW)
SN74ALS651A,
’AS651
SN54ALS652,
SN74ALS652A,
’AS652
’ALS653
SN74ALS654
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
3 State
Open Collector
Open Collector
3 State
3 State
3 State
True
Inverting
True
SN54ALS’, SN54AS’ . . . FK PACKAGE
(TOP VIEW)
description
A1
A2
A3
NC
A4
A5
A6
5
OEAB
SAB
CLKAB
NC
V
CC
CLKBA
SAB
4
3 2 1 28 27 26
25
These devices consist of bus-transceiver circuits,
6
24
B1
D-type flip-flops, and control circuitry arranged for
7
23
B2
multiplexed transmission of data directly from the
8
22
NC
data bus or from the internal storage registers.
9
21
B3
Output-enable (OEAB and OEBA) inputs are
10
20
B4
provided to control the transceiver functions.
11
19
B5
Select-control (SAB and SBA) inputs are provided
12 13 14 15 16 17 18
to select real-time or stored data transfer. The
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
NC – No internal connection
data. A low input level selects real-time data, and
a high input level selects stored data. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the octal bus
transceivers and registers.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
A7
A8
GND
NC
B8
B7
B6
OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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