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SN74AUC2G04DBVR 参数 Datasheet PDF下载

SN74AUC2G04DBVR图片预览
型号: SN74AUC2G04DBVR
PDF下载: 下载PDF文件 查看货源
内容描述: 双非门 [DUAL INVERTER GATE]
分类和应用:
文件页数/大小: 12 页 / 481 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SN74AUC2G04
DUAL INVERTER GATE
SCES437A – APRIL 2003 – REVISED JUNE 2003
D
D
D
D
D
D
D
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max t
pd
of 1.7 ns at 1.8 V
Low Power Consumption, 10
µA
at 1.8 V
±8-mA
Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE
(TOP VIEW)
1A
GND
2A
1
2
3
6
5
4
1Y
V
CC
2Y
YEP OR YZP PACKAGE
(BOTTOM VIEW)
2A
GND
1A
3 4
2 5
1 6
2Y
V
CC
1Y
description/ordering information
This dual inverter is operational at 0.8-V to 2.7-V V
CC
, but is designed specifically for 1.65-V to 1.95-V V
CC
operation.
The SN74AUC2G04 performs the Boolean function Y = A.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40°C 85°C
–40 C to 85 C
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
Tape and reel
Tape and reel
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74AUC2G04YEPR
_ _ _UC_
SN74AUC2G04YZPR
SN74AUC2G04DBVR
SN74AUC2G04DCKR
U04_
UC_
TOP-SIDE
MARKING‡
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1