SN74AUP1G57
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES503D – NOVEMBER 2003 – REVISED JUNE 2005
FEATURES
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Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Low Static-Power Consumption (I
CC
= 0.9
µA
Max)
Low Dynamic-Power Consumption
(C
pd
= 4.3 pF Typ at 3.3 V)
Low Input Capacitance (C
i
= 1.5 pF Typ)
Low Noise – Overshoot and Undershoot <10%
of V
CC
I
off
Supports Partial-Power-Down Mode
Operation
Includes Schmitt-Trigger Inputs
Wide Operating V
CC
Range of 0.8 V to 3.6 V
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
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Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
t
pd
= 5.3 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
ESD Protection Exceeds ±5000 V With
Human-Body Model
DRL PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
In1
GND
In0
1
6
In2
V
CC
Y
In1
GND
1
2
3
6
5
4
In2
V
CC
Y
In1
GND
In0
1
2
3
6
5
4
In2
V
CC
Y
In0
GND
In1
3 4
2 5
1 6
Y
V
CC
In2
2
5
4
In0
3
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire V
CC
range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity,
which produces very low undershoot and overshoot characteristics.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40°C to 85°C
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1)
(2)
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Reel of 4000
ORDERABLE PART NUMBER
SN74AUP1G57YEPR
_ _ _HH_
SN74AUP1G57YZPR
SN74AUP1G57DBVR
SN74AUP1G57DCKR
SN74AUP1G57DRLR
HA7_
HH_
HH_
TOP-SIDE MARKING
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
