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SN74CBT16210CDGG 参数 Datasheet PDF下载

SN74CBT16210CDGG图片预览
型号: SN74CBT16210CDGG
PDF下载: 下载PDF文件 查看货源
内容描述: 20位FET总线开关5 -V总线-2 -V冲保护开关 [20-BIT FET BUS SWITCH 5-V BUS SWITCH WITH -2-V UNDERSHOOT PROTECTION]
分类和应用: 总线驱动器总线收发器开关逻辑集成电路光电二极管
文件页数/大小: 13 页 / 369 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SCDS115C − JANUARY 2003 − REVISED OCTOBER 2003
SN74CBT16210C
20 BIT FET BUS SWITCH
5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50
VG1
50
DUT
7V
Input Generator
50
VG2
VI
50
VO
CL
(see Note A)
RL
RL
S1
Open
GND
TEST CIRCUIT
TEST
tpd(s)
tPLZ/tPZL
tPHZ/tPZH
VCC
5 V
±
0.5 V
4V
5 V
±
0.5 V
4V
5 V
±
0.5 V
4V
S1
Open
Open
7V
7V
Open
Open
RL
500
500
500
500
500
500
VI
VCC or GND
VCC or GND
GND
GND
VCC
VCC
Output
Control
(VIN)
tPZL
CL
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
V
0.3 V
0.3 V
0.3 V
0.3 V
3V
1.5 V
1.5 V
0V
tPLZ
3.5 V
1.5 V
VOL + V
tPHZ
VOH − V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL
Output
Control
(VIN)
tPLH
Output
3V
1.5 V
1.5 V
0V
tPHL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
Output
Waveform 1
S1 at 7 V
(see Note B)
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
Ω,
tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265