SN74GTL2007
12 BIT GTL /GTL/GTL+ TO LVTTL TRANSLATOR
SCLS609 − MARCH 2005
D
Operates as a GTL-/GTL/GTL+ to LVTTL or
D
D
D
LVTTL to GTL-/GTL/GTL+ Translator
Series Termination on TTL Outputs of 30
W
Latch-Up Testing Done to JEDEC Standard
JESD 78
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
V
REF
1AO
2AO
5A
6A
EN1
11BI
11A
9BI
3AO
4AO
10AI1
10AI2
GND
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
description/ordering information
The SN74GTL2007 is a 12-bit translator to
interface between the 3.3-V LVTTL chip set I/O
and the Xeon processor GTL-/GTL/GTL+ I/O.
The device is designed for platform health
management in dual-processor applications.
PIN DESCRIPTION
PIN NUMBER
1
2-6, 8, 10-13,
15, 23
7, 9, 16,
17−22, 24−27
14
28
SYMBOL
VREF
ENn
nAn
nBn
GND
VCC
V
CC
1BI
2BI
7BO1
7BO2
EN2
11BO
5BI
6BI
3BI
4BI
10BO1
10BO2
9AO
NAME AND FUNCTION
GTL reference voltage
Data and enable inputs/outputs (LVTTL)
Data inputs/outputs (GTL−/GTL/GTL+)
Ground (0 V)
Positive supply voltage
ORDERING INFORMATION
TA
−40°C to 85°C
PACKAGE†
TSSOP − PW
Tube
Tape and reel
ORDERABLE
PART NUMBER
SN74GTL2007PW
SN74GTL2007PWR
TOP-SIDE
MARKING
GK2007
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2005, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1