SN54LV163A, SN74LV163A
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS405E − APRIL 1998 − REVISED DECEMBER 2004
D
2-V to 5.5-V V
CC
Operation
D
Max t
pd
of 9.5 ns at 5 V
D
Typical V
OLP
(Output Ground Bounce)
D
D
D
D
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Internal Look Ahead for Fast Counting
Carry Output for n-Bit Cascading
D
Synchronous Counting
D
Synchronously Programmable
D
I
off
Supports Partial-Power-Down Mode
D
D
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV163A . . . FK PACKAGE
(TOP VIEW)
CLR
ENP
GND
NC
LOAD
GND
8
9
NC − No internal connection
description/ordering information
ORDERING INFORMATION
TA
PACKAGE†
QFN − RGY
SOIC − D
SOP − NS
−40°C to 85 C
−40 C 85°C
SSOP − DB
Reel of 1000
Tube of 40
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
TSSOP − PW
TVSOP − DGV
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
ORDERABLE
PART NUMBER
SN74LV163ARGYR
SN74LV163AD
SN74LV163ADR
SN74LV163ANSR
SN74LV163ADBR
SN74LV163APW
SN74LV163APWR
SN74LV163APWT
SN74LV163ADGVR
SNJ54LV163AJ
SNJ54LV163AW
SNJ54LV163AFK
LV163A
SNJ54LV163AJ
SNJ54LV163AW
SNJ54LV163AFK
LV163A
LV163A
74LV163A
LV163A
TOP-SIDE
MARKING
LV163A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
2004, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
LOAD
ENT
CLR
CLK
A
B
C
D
ENP
GND
1
2
3
4
5
6
7
16
15
14
13
12
11
10
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
1
16
15
RCO
14
Q
A
13
Q
B
12
Q
C
11
Q
D
10
ENT
CLK
A
B
C
D
ENP
2
3
4
5
6
7
8
9
A
B
NC
C
D
CLK
CLR
NC
V
CC
RCO
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
V
CC
SN54LV163A . . . J OR W PACKAGE
SN74LV163A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
SN74LV163A . . . RGY PACKAGE
(TOP VIEW)
Q
A
Q
B
NC
Q
C
Q
D
1
TI [ TEXAS INSTRUMENTS ]
