SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3 STATE OUTPUTS
SCLS398G − APRIL 1998 − REVISED APRIL 2005
D
2-V to 5.5-V V
CC
Operation
D
Max t
pd
of 7 ns at 5 V
D
Typical V
OLP
(Output Ground Bounce)
D
D
D
D
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV367A . . . J OR W PACKAGE
SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
2OE
2A2
2Y2
2A1
2Y1
1A4
1Y4
SN54LV367A . . . FK PACKAGE
(TOP VIEW)
description/ordering information
The ’LV367A devices are hex buffers and line
drivers designed for 2-V to 5.5-V V
CC
operation.
These devices are designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
The ’LV367A devices are organized as dual 4-line
and 2-line buffers/drivers with active-low
output-enable (1OE and 2OE) inputs. When OE is
low, the device passes noninverted data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
1Y1
1A2
NC
1Y2
1A3
4
5
6
7
8
1A1
1OE
NC
V
CC
2OE
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2A2
2Y2
NC
2A1
2Y1
NC − No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
SOIC − D
SOP − NS
−40 C 85°C
−40°C to 85 C
SSOP − DB
TSSOP − PW
TVSOP − DGV
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
PACKAGE†
Tube of 40
Reel of 2500
Reel of 2000
Reel of 2000
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
ORDERABLE
PART NUMBER
SN74LV367AD
SN74LV367ADR
SN74LV367ANSR
SN74LV367ADBR
SN74LV367APWR
SN74LV367APWT
SN74LV367ADGVR
SNJ54LV367AJ
SNJ54LV367AW
SNJ54LV367AFK
LV367A
LV367A
SNJ54LV367AJ
SNJ54LV367AW
SNJ54LV367AFK
LV367A
74LV367A
LV36A
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
2005, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
1Y3
GND
NC
1Y4
1A4
1
TI [ TEXAS INSTRUMENTS ]
