SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998
D
D
D
D
D
D
D
EPIC
™
(Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25°C
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
D, DB, OR PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
1C
1Y
3C
3B
3A
3Y
description
This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V V
CC
operation.
The SN74LVC10A performs the Boolean function Y = A
•
B
•
C or Y = A + B + C in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC10A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
X
B
H
X
L
X
C
H
X
X
L
OUTPUT
Y
L
H
H
H
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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