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SN74LVCZ161284AGR 参数 Datasheet PDF下载

SN74LVCZ161284AGR图片预览
型号: SN74LVCZ161284AGR
PDF下载: 下载PDF文件 查看货源
内容描述: 无差错POWER UP 19位IEEE STD 1284转换收发器 [19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
文件页数/大小: 13 页 / 277 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED MAY 2005
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
CABLE
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply voltage range
Supply voltage range
Input and output voltage range
Input clamp current
Output clamp current
Continuous output current
Continuous current through each V
CC
or GND
I
SK
θ
JA
T
stg
(1)
(2)
(3)
(4)
Output high sink current
Package thermal
impedance
(4)
–65
Storage temperature range
V
O
= 5.5 V and V
CC
CABLE = 3 V
Cable side
(2) (3)
Peripheral
V
I
< 0
V
O
< 0
Except PERI LOGIC OUT
PERI LOGIC OUT
side
(2)
–0.5
–0.5
–2
–0.5
MAX
7
4.6
7
V
CC
+ 0.5
–20
–50
±50
±100
±200
65
70
150
UNIT
V
V
V
mA
mA
mA
mA
mA
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The ac input voltage pulse duration is limited to 40 ns if the amplitude is greater than –0.5 V.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
(1)
MIN
V
CC
CABLE
V
CC
Supply voltage for the cable side, V
CC
CABLE
V
CC
Supply voltage
A, B, DIR, and HD
V
IH
High-level input voltage
C14–C17
HOST LOGIC IN
PERI LOGIC IN
A, B, DIR, and HD
V
IL
Low-level input voltage
C14–C17
HOST LOGIC IN
PERI LOGIC IN
V
I
V
O
I
OH
Input voltage
Open-drain output voltage
High-level output current
Peripheral side
Cable side
HD low
HD high, B and Y outputs
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
B and Y outputs
I
OL
T
A
(1)
Low-level output current
Operating free-air temperature
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
0
0
0
0
3
3
2
2.3
2.6
2
0.8
0.8
1.6
0.8
V
CC
5.5
5.5
–14
–4
–0.5
14
4
84
70
°C
mA
mA
V
V
V
V
MAX
5.5
3.6
UNIT
V
V
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
4