SDLS053B − OCTOBER 1976 − REVISED MAY 2004
SN54147, SN54148, SN54LS147, SN54LS148
SN74147, SN74148 (TIM9907), SN74LS147, SN74LS148
10 LINE TO 4 LINE AND 8 LINE TO 3 LINE PRIORITY ENCODERS
description/ordering information
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been provided to allow octal expansion without the need for external
circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent
one normalized Series 54/74 or 54/74LS load, respectively.
ORDERING INFORMATION
TA
PDIP − N
0°C to 70°C
SOIC − D
SOP − NS
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
PACKAGE†
Tube
Tube
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74LS148N
SN74LS148D
SN74LS148DR
SN74LS148NSR
SNJ54LS148J
SNJ54LS148W
SNJ54LS148FK
LS148
74LS148
SNJ54LS148J
SNJ54LS148W
SNJ54LS148FK
TOP-SIDE
MARKING
SN74LS148N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE − ’147, ’LS147
INPUTS
1
H
X
X
X
X
X
X
X
X
L
2
H
X
X
X
X
X
X
X
L
H
3
H
X
X
X
X
X
X
L
H
H
4
H
X
X
X
X
X
L
H
H
H
5
H
X
X
X
X
L
H
H
H
H
6
H
X
X
X
L
H
H
H
H
H
7
H
X
X
L
H
H
H
H
H
H
8
H
X
L
H
H
H
H
H
H
H
9
H
L
H
H
H
H
H
H
H
H
D
H
L
L
H
H
H
H
H
H
H
OUTPUTS
C
H
H
H
L
L
L
L
H
H
H
B
H
H
H
L
L
H
H
L
L
H
A
H
L
H
L
H
L
H
L
H
L
H = high logic level, L = low logic level, X = irrelevant
2
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•
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