DUAL BUFFER GATE
www.ti.com
SCES359H – AUGUST 2001 – REVISED FEBRUARY 2007
FEATURES
•
•
•
•
•
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•
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Max I
CC
±24-mA
Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
•
•
•
•
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25°C
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
1A
GND
2A
1
6
1Y
V
CC
2Y
1A
GND
1
2
3
6
5
4
1Y
V
CC
2Y
1A
GND
2A
1
2
3
6
5
4
1Y
V
CC
2Y
2A
GND
1A
3 4
2 5
1 6
2Y
V
CC
1Y
2
5
2A
3
4
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual buffer gate is designed for 1.65-V to 5.5-V V
CC
operation. The SN74LVC2G34 performs the Boolean
function Y = A in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
–40°C to 85°C
SOT (SC-70) – DCK
SOT (SOT-533) – DRL
(1)
(2)
Reel of 3000
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
ORDERABLE PART NUMBER
SN74LVC2G34YZPR
SN74LVC2G34DBVR
SN74LVC2G34DBVT
SN74LVC2G34DCKR
SN74LVC2G34DCKT
SN74LVC2G34DRLR
TOP-SIDE MARKING
(2)
_ _ _C9_
C34_
C9_
C9_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2007, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
