SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SN65HVD3088E
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2)
UNITS
Supply voltage range, VCC
Voltage range at A or B
Voltage range at any logic pin
Receiver output current
Voltage input range, transient pulse, A and B, through 100
Ω
(see Figure 13)
Junction temperature, TJ
Continuous total power dissipation
−0.5 V to 7 V
−9 V to 14 V
−0.3 V to VCC + 0.3 V
−24 mA to 24 mA
−50 V to 50 V
170°C
Refer to Package Dissipation Table
(1) Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under
recommended operating conditions
is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
PACKAGE
D
P
DGK
JEDEC BOARD MODEL
Low k(1)
High k(2)
Low k(1)
Low k(1)
High k(2)
TA <25°C
POWER RATING
507 mW
824 mW
686 mW
394 mW
583 mW
DERATING FACTOR
(3)
ABOVE TA = 25°C
4.82 mW/°C
7.85 mW/°C
6.53 mW/°C
3.76 mW/°C
5.55 mW/°C
TA = 70°C
POWER RATING
289 mW
471 mW
392 mW
255 mW
333 mW
TA = 85°C
POWER RATING
217 mW
353 mW
294 mW
169 mW
250 mW
(1) In accordance with the low-k thermal metric definitions of EIA/JESD51-3
(2) In accordance with the high-k thermal metric definitions of EIA/JESDS1-7
(3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
2
TI [ TEXAS INSTRUMENTS ]
