TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
MIN
td(TSDR)
td(FSR)
tsu(PCM IN)
th(PCM IN)
tc(DCLKR)
t(SER)
Time-slot delay time from DCLKR (see Note 9)
Frame-sync delay time
Receive data setup time
Receive data hold time
Data clock period
Time-slot end receive time
140
100
50
60
488
0
15620
MAX
td(DCLKR)–140
tc(CLK)–100
UNIT
ns
ns
ns
ns
ns
ns
NOTE 9: tFSLR minimum requirement overrides the td(TSDR) maximum requirement for 64-kHz operation.
64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode
MIN
tFSLX
tFSLR
tw(DCLK)
Transmit frame-sync minimum down time
Receive frame-sync minimum down time
Pulse duration, data clock
FSX = TTL high for remainder of frame
488
1952
10
MAX
UNIT
ns
ns
µs
switching characteristics
delay time over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate
mode (see Figure 3 and 4)
PARAMETER
tpd1
tpd2
tpd3
tpd4
tpd5
tpd6
From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable
time on time-slot entry) (see Note 10)
From rising edge of transmit clock bit n to bit n data valid at PCM OUT (data
valid time)
From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time
on time-slot exit) (see Note 10)
From rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable
time)
From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable
time) (see Note 10)
From rising edge of channel time slot to SIGR update (TCM29C14A and
TCM129C14A only)
TEST CONDITIONS
CL = 0 to 100 pF
CL = 0 to 100 pF
CL = 0
CL = 0 to 100 pF
CL = 0
MIN
0
0
60
0
60
0
MAX
145
145
215
145
190
2
UNIT
ns
ns
ns
ns
ns
µs
NOTE 10: Timing parameters tpd1, tpd3, and tpd5 are referenced to the high-impedance state.
delay time over recommended ranges of operating conditions, variable-data-rate mode (see Note 11 and
Figure 5)
PARAMETER
tpd7
tpd8
tpd9
tpd10
Delay time from DCLKX
Delay from time-slot enable to PCM OUT
Delay from time-slot disable to PCM OUT
Delay time from FSX
td(TSDX) = 80 ns
CL = 0 to 100 pF
TEST CONDITIONS
MIN
0
0
0
0
MAX
100
50
80
140
UNIT
ns
ns
ns
ns
NOTE 11: Timing parameters tpd8 and tpd9 are referenced to the high-impedance state.
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
11
TI [ TEXAS INSTRUMENTS ]
