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30-bit 4:4:4: 1× pixel clock. 4:2:2 to 4:4:4 interpolation should be bypassed. Optional 2× oversampling is
available for formats with pixel clock up to 80 MHz.
20-bit 4:2:2: 1× pixel clock. 4:2:2 to 4:4:4 interpolation should be switched in, and is available for formats
with pixel clock up to 150 MHz. Optional 2× oversampling available for formats with pixel clock up to 80 MHz.
10-bit 4:2:2 (ITU): 1/2× pixel clock. 4:2:2 to 4:4:4 interpolation should be switched in, and is available for
formats with pixel clock up to 150 MHz. Optional 2× oversampling is available for formats with pixel clock
up to 80 MHz.
The internal DLL (delay-locked loop) generates the higher clock frequencies. The user should program the input
frequency range selection register, dll_freq_sel, according to the frequency present on CLK_IN when using either
or both interpolation/oversampling stages.
The 4:2:2 to 4:4:4 stage is switched in or bypassed, depending on the setting of data_ifir12_bypass register
(interpolation only on chroma channels). This feature should only be used with YCbCr 4:2:2 input. The THS8200 can
perform color space conversion to RGB depending on the CSC setting. The dtg2_rgbmode_on register should be
set corresponding to the color space representation of the DAC output.
The 2× oversampling stage is switched in or bypassed, depending on the setting of data_ifir35_bypass register.
The user should not enable the 2× oversampling stage when the CLK_IN frequency exceeds 80 MHz, as is the case
for the higher PC graphics formats and 1080P HDTV. In this case the DLL should be bypassed using the vesa_clk
register to disable the 2× frequency generation. As explained in the detailed register map description for this register,
it is still possible to support 20-bit 4:2:2 input in this mode (e.g., for 1080P).
A second bypass mode operation exists for the DLL, enabled by the dll_bypass register. When this bypass mode is
active, the CLKIN input is assumed to be 2× pixel frequency. This mode is meant only for test purposes as it does
not correspond to any mode in the supported input formats table.
4.4 Color Space Conversion (CSC)
THS8200 contains a fully-programmable 3×3 multiply/add and 3×1 adder block that can be switched in for all video
formats up to a pixel clock frequency of 150 MHz. Color space conversion is thus available for all DTV modes,
including 1080P and VESA modes up to SXGA at 75 Hz (135 MSPS). The operation is done after optional 4:2:2 to
4:4:4 conversion, and thus on the 1× pixel clock video data prior to optional 2× video oversampling. The CSC block
can be switched in or bypassed depending on the setting of register csc_bypass.
Each of the nine floating point multiplier coefficients of the 3×3 multiply/add is represented as the combination of a
6-bit signed binary integer part, and a 10-bit fractional part. The integer part is a signed magnitude representation
with the MSB as the sign bit. The fractional part is a magnitude representation; see the following example.
The register nomenclature is: csc_<r,g,b> <i,f>c<1,2,3> where:
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<r,g,b> identifies which input channel is multiplied by this coefficient (r = red/Cr, g = green/Y, b = blue/Cb
input)
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<i,f> identifies the integer (i) or fractional (f) part of the coefficient
<1,2,3> identifies the output channel from the color space converter: 1 = Yd/Gd, 2 = Cb/Bd, 3 = Cr/Rd
Fortheoffsetvalues, avalueof1/4ofthedesireddigitaloffsetneedstobeprogrammedintheindividualoffsetregister,
so a typical offset of 512 (offset over 1/2 of the video range) requires programming a value of 128 decimal into the
offset<1,2,3> registers, where again <1,2,3> defines the output channel affected, with similar convention as shown
previously.
Saturation logic can be switched in to avoid over- and underflow on the result after color space conversion using the
csc_uof_cntl register.
We next show an example of how to program the CSC. This also explains the numeric data formats.
CSC configuration example: HDTV RGB to HDTV YCbCr
4–6
TI [ TEXAS INSTRUMENTS ]
