TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
Terminal Functions
TERMINAL
NAME
AIN0 – AIN10
NO.
1 – 9,
11, 12
15
I/O
I
DESCRIPTION
Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should
be less than or equal to 50
Ω
for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input
voltage into a capacitance of 60 pF.
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,
DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup
time.
Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next.
The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK.
After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order.
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state
and is driven to the logic level corresponding to the MSB/LSB† value of the previous conversion result. The
next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and
the remaining bits are shifted out in order.
End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and
remains low until the conversion is complete and the data is ready for transfer.
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.
I
Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of the I/O
CLOCK.
3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of I/O CLOCK.
4. It transfers control of the conversion to the internal state controller on the falling edge of the last
I/O CLOCK.
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The
maximum input voltage range is determined by the difference between the voltage applied to this terminal and
the voltage applied to the REF – terminal.
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF –.
CS
I
DATA INPUT
17
I
DATA OUT
16
O
EOC
GND
I/O CLOCK
19
10
18
O
REF +
14
I
REF –
13
I
VCC
20
Positive supply voltage
† MSB/LSB = Most significant bit /least significant bit
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•
DALLAS, TEXAS 75265
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TI [ TEXAS INSTRUMENTS ]
