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TMS320LF2407PGEA 参数 Datasheet PDF下载

TMS320LF2407PGEA图片预览
型号: TMS320LF2407PGEA
PDF下载: 下载PDF文件 查看货源
内容描述: DSP控制器 [DSP CONTROLLERS]
分类和应用: 控制器
文件页数/大小: 115 页 / 1498 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320LF2407, TMS320LF2406, TMS320LF2402
DSP CONTROLLERS
SPRS094I − APRIL 1999 − REVISED SEPTEMBER 2003
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TMS320LF2407, TMS320LF2406, and
TMS320LF2402 are Being Replaced by
TMS320LF2407A, TMS320LF2406A, and
TMS320LF2402A, Respectively. Hence,
TMS320LF2407, TMS320LF2406, and
TMS320LF2402 are NOT RECOMMENDED
FOR NEW DESIGNS (NRND).
High-Performance Static CMOS Technology
− 33-ns Instruction Cycle Time (30 MHz)
− 30-MIPS Performance
− Low-Power 3.3-V Design
Based on TMS320C2xx DSP CPU Core
− Code-Compatible With F243/F241/C242
− Instruction Set and Module Compatible
With F240/C240
On-Chip Memory
− Up to 32K Words x 16 Bits of Flash
EEPROM (4 Sectors)
− Up to 2.5K Words x 16 Bits of
Data/Program RAM
− 544 Words of Dual-Access RAM
− Up to 2K Words of Single-Access RAM
Boot ROM
− SCI/SPI Bootloader
Two Event-Manager (EV) Modules (EVA and
EVB), Each Include:
− Two 16-Bit General-Purpose Timers
− Eight 16-Bit Pulse-Width Modulation
(PWM) Channels Which Enable:
− Three-Phase Inverter Control
− Center- or Edge-Alignment of PWM
Channels
− Emergency PWM Channel Shutdown
With External PDPINTx Pin
− Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults
− Three Capture Units For Time-Stamping
of External Events
− On-Chip Position Encoder Interface
Circuitry
− Synchronized Analog-to-Digital
Conversion
− Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control
− Applicable for Multiple Motor and/or
Converter Control
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External Memory Interface (LF2407)
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− 192K Words x 16 Bits of Total Memory:
64K Program, 64K Data, 64K I/O
Watchdog (WD) Timer Module
10-Bit Analog-to-Digital Converter (ADC)
− 8 or 16 Multiplexed Input Channels
− 500 ns Minimum Conversion Time
− Selectable Twin 8-Input Sequencers
Triggered by Two Event Managers
Controller Area Network (CAN) 2.0B Module
Serial Communications Interface (SCI)
16-Bit Serial Peripheral Interface (SPI)
Module
Phase-Locked-Loop (PLL)-Based Clock
Generation
Up to 40 Individually Programmable,
Multiplexed General-Purpose Input / Output
(GPIO) Pins
Up to Five External Interrupts (Power Drive
Protection, Reset, and Two Maskable
Interrupts)
Power Management:
− Three Power-Down Modes
− Ability to Power Down Each Peripheral
Independently
Real-Time JTAG-Compliant Scan-Based
Emulation, IEEE Standard 1149.1
(JTAG)
Development Tools Include:
− Texas Instruments (TI) ANSI C Compiler,
Assembler/ Linker, and Code Composer
Studio Debugger
− Evaluation Modules
− Scan-Based Self-Emulation (XDS510)
− Broad Third-Party Digital Motor Control
Support
Package Options
− 144-Pin Low-Profile Quad Flatpack
(LQFP) PGE (LF2407)
− 100-Pin LQFP PZ (LF2406)
− 64-Pin Quad Flatpack (QFP) PG (LF2402)
Extended Temperature Options (A and S)
− A: − 40°C to 85°C
− S: − 40°C to 125°C
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio and XDS510 are trademarks of Texas Instruments.
† IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
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