TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
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Highest Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6201
– 6-, 5-ns Instruction Cycle Time
– 167-, 200-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1336, 1 600 MIPS
Highest Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6201B
– 5-, 4.3-ns Instruction Cycle Time
– 200-, and 233-MHz Clock Rates
– Eight 32-Bit Instructions/Cycle
– 1600, 1 860 MIPS
VelociTI™ Advanced Very Long Instruction
Word (VLIW) ’C62x CPU Core
– Eight Independent Functional Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Results)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
– 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as a Single Block
(’6201)
– 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency (’6201B)
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
GJC/GJL/GGP
352-PIN BALL GRID ARRAY (BGA) PACKAGES
(BOTTOM VIEW)
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16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial Peripheral Interface (SPI)
Compatible (Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG
†
) Boundary-Scan
Compatible
352-Pin BGA Package (GGP Suffix) (’6201)
352-Pin BGA Package (GJC Suffix) (’6201B)
352-Pin BGA Package (GJL Suffix) (’6201B)
CMOS Technology
– 0.25-µm/5-Level Metal Process (’6201)
– 0.18-µm/5-Level Metal Process (’6201B)
3.3-V I/Os, 2.5-V Internal (’6201)
3.3-V I/Os, 1.8-V Internal (’6201B)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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1999, Texas Instruments Incorporated
•
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