TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
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Supports Provisions of IEEE 1394-1995
(1394) Standard for High-Performance
Serial Bus
†
Fully Interoperable With FireWire™
Implementation of 1394
Provides A Backplane Environment That
Supports 50 or 100 Megabits per Second
(Mbits/s)
Logic Performs System Initialization and
Arbitration Functions
Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding
Incoming Data Resynchronized to Local
Clock
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Separate Transmitter and Receiver for
Greater Flexibility
Data Interface to Link-Layer Controller
(Link) Provided Through Two Parallel
Signal Lines at 25/50 MHz
100-MHz or 50-MHz Oscillator Provides
Transmit, Receive-Data, and Link Clocks at
25/50 MHz
Single 5-V Supply Operation
Packaged in a High-Performance 64-Pin
TQFP (PM) Package for 0°C to 70°C
Operation and – 40°C to 85°C Operation
Packaged in a 68-Pin CFP (HV) Package for
– 55°C to 125°C Operation
description
The TSB14C01A provides the transceiver functions needed to implement a single port node in a backplane-
based 1394 network. The TSB14C01A provides two terminals for transmitting, two terminals for receiving, and
a single terminal to externally control the drivers for data and strobe. The TSB14C01A is not designed to drive
the backplane directly, this function must be provided externally. The TSB14C01A is designed to interface with
a link-layer controller (link), such as the TSB12C01A.
The TSB14C01A requires an external 98.304-MHz or 49.152-MHz reference oscillator input for S100/50
operation. The reference signal is internally divided to provide the 49.152-MHz
±100-ppm
system clock signals
used to control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock
signal is supplied to the associated link for synchronization of the two chips. When this device is in the S100
mode of operation, OSC_SEL is asserted high. When the TSB14C01A is in the S50 mode of operation, the clock
rate supplied to the link is 24.576 MHz.
Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the
TSB14C01A in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded,
and then transmitted at 98.304-Mbits/s (in S100 mode) as the outbound data-strobe information stream. During
transmission, the encoded data information is transmitted on TDATA, and the encoded strobe information is
transmitted on TSTRB.
During packet reception the encoded information is received on RDATA and strobe information on RSTRB. The
received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The
serial data bits are split into two parallel streams, resynchronized to the local system clock, and sent to the
associated link.
The TSB14C01A is a 5-V device and provides CMOS-level outputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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