UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, C
VREF
= 0.47
mF,
VDD = 12V. T
A
= T
J
.
:
PARAMETER
Soft Start Section
I
SS
TEST CONDITIONS
VDD = 16V, V
SS
= 0V; –40°C to
+85°C
VDD = 16V, V
SS
= 0V;
<
–40°C;
>+85°C
VDD = 7.5V, I
SS
= 200mA
MIN
–4.9
–4.0
0.44
90
TYP
–7.0
–7.0
0.48
100
0.1
3.33
1.67
1.67
0.8
0.8
0
70
35
18
MAX
–9.1
–10.0
0.2
0.52
110
UNIT
mA
mA
V
V
kHz
%/V
V
V
V
V
V
V
%
%
ns
ns
V
SS
Low
Shutdown Threshold
Oscillator Section
Frequency
RT1 = 10k, RT2 = 4.32k, CT = 820pF
Frequency Change with Voltage
VDD = 10V to 15V
C
T
Peak Voltage
C
T
Valley Voltage
C
T
Peak to Peak Voltage
Output Section
I
OUT
= 80mA (dc)
Output V
SAT
Low
I
OUT
= –40mA (dc), VDD – OUT
Output V
SAT
High
Output Low Voltage During UVLO
I
OUT
= 20mA (dc)
Minimum Duty Cycle
V
FB
= 2V
Maximum Duty Cycle
Rise Time
C
OUT
= 1nF
Fall Time
C
OUT
= 1nF
Note 1. Ensured by design. Not 100% production tested.
1.54
1.80
1.5
1.5
1.5
PIN DESCRIPTIONS
FB:
This pin is the summing node for current sense
feedback, voltage sense feedback (by optocoupler) and
slope compensation. Slope compensation is derived
from the rising voltage at the timing capacitor and can be
buffered with an external small signal NPN transistor.
External high frequency filter capacitance applied from
this node to GND is discharged by an internal 250W on
resistance NMOS FET during PWM off time and offers
effective leading edge blanking set by the RC time
constant of the feedback resistance from current sense
resistor to FB input and the high frequency filter capacitor
capacitance at this node to GND.
GND:
Reference ground and power ground for all
functions.
OUT:
This pin is the high current power driver output. A
minimum series gate resistor of 3.9W is recommended to
limit the gate drive current when operating with high bias
voltages.
REF:
The internal 5V reference output. This reference is
buffered and is available on the REF pin. REF should be
bypassed with a 0.47mF ceramic capacitor.
RT1:
This pin connects to timing resistor RT1 and
controls the positive ramp time of the internal oscillator
(Tr = 0.74
·
(C
T
+ 27pF)
·
RT1). The positive threshold of
the internal oscillator is sensed through inactive timing
resistor RT2 which connects to pin RT2 and timing
capacitor C
T
.
3
RT2:
This pin connects to timing resistor RT2 and
controls the negative ramp time of the internal oscillator
(Tf = 0.74
·
(C
T
+ 27pF)
·
RT2). The negative threshold
of the internal oscillator is sensed through inactive timing
resistor RT1 which connects to pin RT1 and timing
capacitor C
T
.
SS:
This pin serves two functions. The soft start timing
capacitor connects to SS and is charged by an internal
6µA current source. Under normal soft start SS is
discharged to at least 0.4V and then ramps positive to 1V
during which time the output driver is held low. As SS
charges from 1V to 2V soft start is implemented by an
increasing output duty cycle. If SS is taken below 0.5V,
the output driver is inhibited and held low. The user
accessible 5V voltage reference also goes low and I
VDD
< 100mA.
VDD:
The power input connection for this device. This
pin is shunt regulated at 17.5V which is sufficiently below
the voltage rating of the DMOS output driver stage. VDD
should be bypassed with a 1mF ceramic capacitor.
TI [ TEXAS INSTRUMENTS ]
