UCC2897
SLUS591A − NOVEMBER 2003 − REVISED MARCH 2004
FUNCTIONAL DESCRIPTION
As the controller starts operation it draws its bias power from the C
BIAS
capacitor until the bootstrap winding
takes over. During this time VDD voltage is falling rapidly as the JFET is already off but the bootstrap voltage
is still not sufficient to power the control circuits. It is imperative to store enough energy in C
BIAS
to prevent the
bias voltage to dip below the turn off threshold of the UVLO circuit during the start up time interval. Otherwise
the power supply goes through several cycles of retry attempts before steady state operation might be
established.
During normal operation the bias voltage is determined by the bootstrap bias design. The UCC2897 can tolerate
a wide range of bias voltages between the minimum operating voltage (UVLO turn-off threshold) and the
absolute maximum operating voltage as defined in the datasheet (14 V).
In applications where the power supply must be able to go to stand by in response to an external command,
the bias voltage of the controller must be kept alive to be able to react intelligently to the control signal. In stand
by mode, switching action is suspended for an undefined period of time and the bootstrap power is unavailable
to bias the controller. Without an alternate power source the bias voltage would collapse and the controller would
initiate a re-start sequence. To avoid this situation, the on board JFET of the UCC2897 controller can keep the
VDD bias alive as long as the gate drive outputs remain inactive. As shown in the timing diagram, the JFET is
turned on when VDD = 10 V and charges the C
BIAS
capacitor to approximately 13.5 V. At that time the JFET
turns off and VDD gradually decreases to 10 V then the procedure is repeated. When the power supply is
enabled again, the controller is fully biased and ready to initiate its soft start sequence. As soon as the gate drive
pulses appear the JFET are turned off and bias must be provided by the bootstrap bias generator.
During power down the situation is different as switching action might continue until the VDD bias voltage drops
below the controller’s own UVLO turn-off threshold (approximately 8 V). At that time the UCC2897 shuts down
completely turning off its 5 V bias rail and returning to start up state when the JFET device is turned on and the
C
BIAS
capacitor starts charging again. In case the converter’s input voltage is re-established, the UCC2897
attempts to restart the converter.
Line Undervoltage Protection
When the input power source is removed the power supply is turned off by the line undervoltage protection
because the bootstrap winding keeps the VDD bias up as long as switching takes place in the power stage. As
the power supply’s input voltage gradually decreases towards the line cut off voltage the converter’s operating
duty cycle must compensate for the lower input voltage. At minimum input voltage the duty cycle nears its
maximum value (D
MAX
). Under these conditions the voltage across the clamp capacitor approaches its highest
value since the transformer must be reset in a relatively short time. The timing diagram in Figure 2 highlights
that in the instance when the converter stops switching the clamp capacitor voltage might be at its maximum
level. Since the clamp capacitor’s only load is the power transformer, this high voltage could linger across the
clamp capacitor for a long time when the converter is off. With this high voltage present across the clamp
capacitor a soft start would be very dangerous. Due to the narrow duty cycle of the main switch and the long
on-time of the clamp switch, easily cauing the power transformer to saturate during soft-start.
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