UCC3912
PIN DESCRIPTIONS
grammed fault level. When set to logic high, the maxi-
mum sourcing current will be a constant 4A for
applications which require fast charging of load capaci-
tance.
B0 - B3: These pins provide digital input to the DAC
which sets the fault current threshold. They can be used
to provide a digital soft-start, adaptive current limiting.
CT: A capacitor connected to ground sets the maximum
fault time. The maximum fault time must be more than
the time to charge the external capacitance in one cycle.
The maximum fault time is defined as FAULT = 27.8 •103
• CT. Once the fault time is reached the output will shut-
down for a time given by: TSD = 833 •103 • CT, this
equates to a 3% duty cycle.
SHTDWN: When this pin is brought to a logic low, the IC
is put into a sleep mode drawing typically less than 1µA
of ICC. The input threshold is hysteretic, allowing the user
to program a start-up delay with an external RC circuit.
VIN: Input voltage to the UCC3912. The recommended
voltage range is 3 to 8 volts. Both VIN pins should be
connected together and to the power source.
FAULT: Open drain output which pulls low upon any con-
dition which causes the output to open: Fault, Thermal
Shutdown, or Shutdown.
VOUT: Output voltage from the UCC3912. When
switched the output voltage will be approximately VIN -
(0.15Ω • IOUT). Both VOUT pins should be connected to-
gether and to the load.
IMAX: When this pin is set to logic low the maximum
sourcing current will always be 1A above the pro-
APPLICATION INFORMATION
4
12
13
5
GND
HEAT SINK
GND PINS
V
V
OUT
IN
2
14
15
VIN
VOUT
R1
C
R
L
C
OUT
IN
3
D1
UCC3912
LED
R
V
SD
IN
S6
16 FAULT
11 CT
SHTDWN
1
C
SD
B0
B1
7
B2
8
B3 IMAX
C
T
6
9
5
V
IN
DIP
SWITCH
S1
S2
S3
S4
S5
UDG-99171
Note: For demonstration board schematic see Design Note DN-58.
Figure 1. Evaluation circuit.
• Reducing the power distribution inductance (e.g., twist
the “+” and “–” leads of the power supply feeding VIN,
locate the power supply close to the UCC3912, use a
PCB ground plane,...etc.).
Protecting The UCC3912 From Voltage Transients
The parasitic inductance associated with the power distri-
bution can cause a voltage spike at VIN if the load current
is suddenly interrupted by the UCC3912. It is important to
limit the peak of this spike to less than 8V to prevent
damage to the UCC3912. This voltage spike can be mini-
mized by:
• Decoupling VIN with a capacitor, CIN (refer to Fig. 1),
located close to pins 2 and 3. This capacitor is typically
less than 1µF to limit the inrush current.
• Clamping the voltage at VIN below 8V with a Zener
diode, D1(refer to Fig. 1), located close to pins 2 and 3.
4
TI [ TEXAS INSTRUMENTS ]
