XIO2221
SCPS216A–JULY 2009–REVISED FEBRAURY 2010
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MAX UNIT
11.7 Electrical Characteristics Over Recommended Operating Conditions (PHY Port
Driver)
PARAMETER
1394a differential output voltage
1394b differential output voltage
TEST CONDITIONS
56 Figure 11-1
MIN
TYP
172
265
mV
VOD
IDIFF
700
Driver difference current (TPA+, TPA–, TPB+,
TPB–)
Drivers enabled, speed signaling off
S200 speed signaling enabled
1.05(1)
4.84(2)
12.4(2)
1.05(1)
mA
mA
mA
ISP20 Common-mode speed signaling current (TPB+,
2.53(2)
TPB–)
0
ISP40 Common-mode speed signaling current (TPB+,
S400 speed signaling enabled
Drivers disabled
8.1(2)
20
TPB–)
0
VOFF Off-state differential voltage
VCM 1394b common-mode voltage
mV
V
1.5
(1) Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to algebraic sum of TPB+ and TPB– driver
currents.
(2) Limits defined as absolute limit of each of TPB+ and TPB– driver currents.
TPAx+
TPBx+
56 W
TPAx-
TPBx-
Figure 11-1. Test Load Diagram
11.8 Switching Characteristics for PHY Port Driver
PARAMETER
TEST CONDITIONS
Between TPA and TPB
MIN
MAX
0.15
0.1
UNIT
ns
Jitter, transmit
Skew, transmit
Between TPA and TPB
10% to 90%, at 1394 connector
90% to 10%, at 1394 connector
50% to 50%
ns
tr
tf
TP differential rise time, transmit
TP differential fall time, transmit
0.5
0.5
2.5
1.2
ns
1.2
ns
Setup time, CTL0, CTL1, D1-D7, LREQ until
PCLK - 1394a-2000
ns
tsu
th
Hold time, CTL0, CTL1, D1-D7, LREQ after PCLK 50% to 50%
- 1394a-2000
0
2.5
1
ns
ns
ns
ns
Setup time, CTL0, CTL1, D1-D7, LREQ until
PCLK - 1394b
50% to 50%
tsu
Hold time, CTL0, CTL1, D1-D7, LREQ after PCLK 50% to 50%
- 1394b
th
td
Delay time, PCLK until CTL0, CTL1, D1-D7, PINT 50% to 50%
0.5
7
192
Electrical Characteristics
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