XTR105P 参数 Datasheet PDF下载

ABSOLUTE MAXIMUM RATINGS

(1)

Power Supply, V+ (referenced to the I

O

pin) ...................................... 40V

Input Voltage, V

IN+

, V

IN–

(referenced to the I

O

pin) .................... 0V to V+

Storage Temperature Range ......................................... –55°C to +125°C

Lead Temperature (soldering, 10s) ............................................... +300°C

Output Current Limit ................................................................ Continuous

Junction Temperature .................................................................... +165°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PACKAGE/ORDERING INFORMATION

(1)

PACKAGE

DESIGNATOR

N

SPECIFIED

TEMPERATURE

RANGE

–40°C to +85°C

PACKAGE

MARKING

XTR105PA

XTR105P

XTR105UA

XTR105UA

XTR105U

XTR105U

ORDERING

NUMBER

XTR105PA

XTR105P

XTR105UA

XTR105UA/2K5

XTR105U

XTR105U/2K5

TRANSPORT

MEDIA, QUANTITY

Rails, 25

Rails, 25

Rails, 58

Tape and Reel, 2500

Rails, 58

Tape and Reel, 2500

PRODUCT

XTR105

PACKAGE-LEAD

DIP-14

"

XTR105

"

SO-14 Surface-Mount

"

D

"

–40°C to +85°C

"

XTR105

"

SO-14 Surface-Mount

"

D

"

–40°C to +85°C

"

"

"

"

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

Top View

DIP and SO

V

LIN

I

R1

12

1

I

R2

14

800µA

800µA

V

REG

V+

11

10

V

IN

+

I

R1

V

IN

R

G

B

1

2

3

4

5

6

7

14 I

R2

13 V

IN

12 V

LIN

11 V

REG

10 V+

9

8

B (Base)

E (Emitter)

+

13

4

R

LIN

1kΩ

R

G

3

2

I = 100µA +

V

IN

R

G

5.1V

–

100µA

9

Q

1

R

G

NC

E

8

I

RET

I

O

V

IN

–

975Ω

25Ω

NC = No Internal Connection

7

40

(

R

)

G

I

O

= 4mA + V

IN

•

6

I

RET

2

XTR105

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