tm
TE
CH
Preliminary T14L1024A
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the
outputs should not be applied.
2. The data output from
D
OUT
are the same as the data written to
D
IN
during the write cycle.
3.
D
OUT
provides the read data for the next address.
4. Transition is measured
±
500 mV from steady state with
C
L
= 5pF.
guaranteed but not 100% tested.
This parameter is
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of
tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the
required tDW. If OE is high during a WE controlled write cycle, this requirement does
not apply and the write pulse can be as short as the specified tWP.
TM Technology, Inc. reserves the right
to change products or specifications without notice.
P. 7
Publication Date: SEP. 2002
Revision:0.F
TMT [ TAIWAN MEMORY TECHNOLOGY ]
