XC6109
Series
■OPERATIONAL
EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.
①
As an early state, the input voltage pin is applied sufficiently high voltage to the release voltage and the delay capacitance
(Cd) is charged to the input pin voltage. While the input pin voltage (V
IN
) starts dropping to reach the detect voltage
(V
DF
) (V
IN
> V
DF
), the output voltage (V
OUT
) keeps the “High” level (=V
IN
).
②
When the input pin voltage keeps dropping and becomes equal to the detect voltage (V
IN
= V
DF
), an N-ch transistor for
the delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit,
which uses the delay capacitance pin as power input, the reference voltage operates as a comparator of V
IN
, and the
output voltage changes into the “Low” level (≦V
IN
×0.1).
The detect delay time (T
DF
) is defined as time which ranges
from V
IN
=V
DF
to the V
OUT
of “Low” level (especially, when the Cd pin is not connected: T
DF0
).
③
While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the
ground voltage (=V
SS
) level. Then, the output voltage (V
OUT)
maintains the “Low” level.
④
While the input pin voltage drops to 0.7V or less and it increases again to 0.7V or more, the output voltage may not be
able to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the
output pin voltage is defined as unstable operating voltage (V
UNS)
.
⑤
While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (V
IN
＜V
DF
+V
HYS
), the
output voltage (V
OUT)
maintains the “Low” level.
⑥
When the input pin voltage continues to increase more than 0.7V up to the release voltage level (= V
DF
+ V
HYS
), the N-ch
transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging
via a delay resistor (Rdelay). The internal circuit, which uses the delay capacitance pin as power input, will operate as a
hysteresis comparator (Rise Logic Threshold: V
TLH
=V
TCD
, Fall Logic Threshold: V
THL
=V
SS
) while the input pin voltage
keeps higher than the detect voltage (V
IN
> V
DF
).
⑦
While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the
delay capacitance (Cd) will be charged up to the input pin voltage. When the delay capacitance pin voltage (V
CD
)
reaches to the delay capacitance pin threshold voltage (V
TCD
), the output voltage changes into the “High” (=V
IN
) level.
T
DR
is defined as time which ranges from V
IN
=V
DF
+V
HYS
to the V
OUT
of “High” level (especially when the Cd pin is not
connected: T
DR0
). T
DR
can be given by the formula (1).
T
DR
=
−
Rdelay
×
Cd
×
In (1
−
V
TCD
/ V
IN
) +T
DR0
…(1)
* In = a natural logarithm
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin threshold voltage is V
IN /2
(TYP.)
TDR=Rdelay
×
Cd
×
0.69
…
(2)
* Rdelay is 2.0MΩ(TYP.)
As an example, presuming that the delay capacitance is 0.68μF, TDR is :
2.0
×
10
6
×
0.68
×
10
-6
×
0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground
(=V
SS
) level because time described in
③
is short.
⑧
While the input pin voltage is higher than the detect voltage (V
IN
> V
DF
), therefore, the output voltage maintains the
“High”(=V
IN
) level.
●Release
Delay Time Chart
Delay Capacitance [Cd]
(μF)
0.01
0.022
0.047
0.1
0.22
0.47
1
Release Delay Time [T
DR
] (TYP.)
(ms)
13.8
30.4
64.9
138
304
649
1380
Release Delay Time [T
DR
] (MIN. ~ MAX.)
(ms)
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243~ 364
519 ~ 778
1100 ~ 1660
7/14
TOREX [ TOREX SEMICONDUCTOR ]
