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TC74HCT74AF 参数 Datasheet PDF下载

TC74HCT74AF图片预览
型号: TC74HCT74AF
PDF下载: 下载PDF文件 查看货源
内容描述: 带预置和清除两个D型触发器 [Dual D-Type Flip Flop with Preset and Clear]
分类和应用: 触发器锁存器逻辑集成电路光电二极管
文件页数/大小: 8 页 / 309 K
品牌: TOSHIBA [ TOSHIBA SEMICONDUCTOR ]
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TC74HCT74AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HCT74AP,TC74HCT74AF,TC74HCT74AFN
Dual D-Type Flip Flop with Preset and Clear
The TC74HCT74A is a high speed CMOS D FLIP FLOP
fabricated with silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL , NMOS and CMOS output voltage levels.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CLOCK
pulse.
CLEAR
and
PRESET
are independent of the CLOCK and
are accomplished by setting the applopriate input to an “L” level.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HCT74AP
TC74HCT74AF
Features
High speed: f
max
= 53 MHz (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 2
μA
(max) at Ta = 25°C
Compatible with TTL outputs: V
IH
= 2 V (min)
V
IL
= 0.8 V (max)
Wide interfacing ability: LSTTL, NMOS, CMOS
Output drive capability: 10 LSTTL loads
Symmetrical output impedance: |I
OH
| = I
OL
= 4 mA (min)
Balanced propagation delays: t
pLH
t
pHL
Pin and function compatible with 74LS74
TC74HCT74AFN
Pin Assignment
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
SOL14-P-150-1.27
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.12 g (typ.)
1
2007-10-01