TMC260 and TMC261 DATASHEET (Rev. 2.05 / 2012-NOV-05)
26
7 STEP/DIR Interface
The STEP and DIR inputs provide a simple, standard interface compatible with many existing motion
controllers. The microPlyer STEP pulse interpolator brings the smooth motor operation of high-
resolution microstepping to applications originally designed for coarser stepping and reduces pulse
bandwidth.
7.1 Timing
Figure 7.1 shows the timing parameters for the STEP and DIR signals, and the table below gives their
specifications. When the DEDGE mode bit in the DRVCTRL register is set, both edges of STEP are
active. If DEDGE is cleared, only rising edges are active. STEP and DIR are sampled and synchronized
to the system clock. An internal analog filter removes glitches on the signals, such as those caused by
long PCB traces. If the signal source is far from the chip, and especially if the signals are carried on
cables, the signals should be filtered or differentially transmitted.
DIR
tSH
tSL
tDSH
tDSU
STEP
Figure 7.1 STEP and DIR timing.
STEP and DIR Interface Timing AC-Characteristics
clock period is tCLK
Parameter
Symbol Conditions
Min
Typ
Max
½ fCLK
¼ fCLK
fCLK/512
Unit
Step frequency (at maximum
microstep resolution)
fSTEP
DEDGE=0
DEDGE=1
Fullstep frequency
STEP input low time
fFS
tSL
max(tFILTSD
tCLK+20)
max(tFILTSD
tCLK+20)
,
,
ns
ns
STEP input high time
tSH
DIR to STEP setup time
DIR after STEP hold time
STEP and DIR spike filtering
time
tDSU
tDSH
20
20
36
ns
ns
ns
tFILTSD Rising and falling
60
85
edge
STEP and DIR sampling relative
to rising CLK input
tSDCLKHI Before rising edge
of CLK
tFILTSD
ns
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