TMC262 DATASHEET (Rev. 2.07 / 2013-FEB-14)
18
Figure 6.2 shows the interfaces in a typical application. The SPI bus is used by an embedded MCU to
initialize the control registers of both a motion controller and one or more motor drivers. STEP/DIR
interfaces are used between the motion controller and the motor drivers.
6.4 Register Write Commands
An SPI bus transaction to the TMC262 is a write command to one of the five write-only registers that
hold configuration parameters and mode bits:
Register
Description
The DRVCTRL register has different formats for controlling the
interface to the motion controller depending on whether or
not the STEP/DIR interface is enabled.
Driver Control Register
(DRVCTRL)
Chopper Configuration Register
(CHOPCONF)
The CHOPCONF register holds chopper parameters and mode
bits.
coolStep Configuration Register
(SMARTEN)
stallGuard2 Configuration Register
(SGCSCONF)
The SMARTEN register holds coolStep parameters and a mode
bit. (smartEnergy is an earlier name for coolStep.)
The SGCSCONF register holds stallGuard2 parameters and a
mode bit.
The DRVCONF register holds parameters and mode bits used to
control the power MOSFETs and the protection circuitry. It also
holds the SDOFF bit which controls the STEP/DIR interface and
the RDSEL parameter which controls the contents of the
response returned in an SPI transaction
Driver Configuration Register
(DRVCONF)
In the following sections, multibit binary values are prefixed with a % sign, for example %0111.
6.4.1 Write Command Overview
The table below shows the formats for the five register write commands. Bits 19, 18, and sometimes
17 select the register being written, as shown in bold. The DRVCTRL register has two formats, as
selected by the SDOFF bit. Bits shown as 0 must always be written as 0, and bits shown as 1 must
always be written with 1. Detailed descriptions of each parameter and mode bit are given in the
following sections.
Register/
Bit
DRVCTRL
DRVCTRL
CHOPCONF
SMARTEN
SGCSCONF
DRVCONF
(SDOFF=1)
(SDOFF=0)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
1
1
TST
PHA
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
PHB
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
TBL1
TBL0
CHM
SFILT
0
SEIMIN
SEDN1
SEDN0
0
SEMAX3
SEMAX2
SEMAX1
SEMAX0
0
SEUP1
SEUP0
0
SEMIN3
SEMIN2
SEMIN1
SEMIN0
SLPH1
SLPH0
SLPL1
SLPL0
0
DISS2G
TS2G1
TS2G0
SDOFF
VSENSE
RDSEL1
RDSEL0
0
SGT6
SGT5
SGT4
SGT3
SGT2
SGT1
SGT0
0
RNDTF
HDEC1
HDEC0
HEND3
HEND2
HEND1
HEND0
HSTRT2
HSTRT1
HSTRT0
TOFF3
TOFF2
TOFF1
TOFF0
0
0
INTPOL
DEDGE
0
0
0
0
0
0
CS4
CS3
CS2
CS1
CS0
MRES3
MRES2
MRES1
MRES0
0
0
0
0
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